In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal car...

The defect-free IDDQ has two major components: (i) the reverse biased p-n junction leakage current, and (ii) the transistor sub-threshold leakage (off) current. The reverse biased p-n junction leakage current can be further divided into two segments: state dependent, and state independent. The state dependent component p-n junction leakage current depends on the reverse biasing of the p-n junct...

For next generation mixed signal ICs, the integration of Design-for-Testability and Built-In Self-Test structures is expected to be of crucial importance for satisfying quality and economic demands. The judgment and evaluation of such testability optimisations, however, requires a better understanding of circuit specific failure modes in deep sub-micron technologies. This paper presents fault s...

Rising levels and spread in IDDQ values render single threshold IDDQ testing obsolete for highperformance chips for deep sub-micron technologies. Increased inter-die and intra-die variations cause unacceptable yield loss with a single pass/fail limit. Use of spatial information to estimate fault-free IDDQ is investigated. Flush delay information is used to refine this estimate under varying pro...

The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Applica...

We present a simple and accurate model to compute the power dissipated in sub-micron CMOS buffers driving RC interconnect lines. The expression obtained accounts for the main effects in current sub-micron CMOS technologies as carrier velocity saturation effects, input-output coupling capacitor, output load, input slew time, device sizes and interconnect resistance. Results are compared to HSPIC...

Analysis and Optimization under Crosstalk and Variability in Deep Sub-Micron VLSI Circuits

Photonic crystals have been widely investigated since they have great potential to manipulate the flow of light in an ultra-compact-scale and enable numerous innovative applications. 2D slab photonic crystals for the telecommunication C band at around 1550 nm have multi-scale structures that are typically micron-scale waveguides and deep sub-micron-scale air hole arrays. Several steps of nanoli...

It is generally known that active pixel sensors (APS) have a number of advantages over CCD detectors if it comes to cost for mass production, power consumption and ease of integration. Nevertheless, most space applications still use CCD detectors because they tend to give better performance and have a successful heritage. To this respect a change may be at hand with the advent of deep sub-micro...