In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifeti...

A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was s...

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility ...

In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of ...

A two-dimensional analytical model for the potential distribution along the bottom channel of the fully depleted region of dual material gate (DMG) SOI MESFET is presented. The potential distribution is modeled by solving the Poisson equation with proper boundary conditions. The model for the potential distribution is extended to derive an analytical expression for the threshold voltage. The ac...

The parametric variations of FinFET in 22 nm due to doping concentrations are presented. In this paper different parameters of FinFET such as subthreshold slope, DIBL, threshold voltage, transconductance and Ioff are analysed using Synopsys Sentaurus 3D TCAD. From the results, it can be concluded that, optimized doping leads to better characteristics for the FinFET.

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field...

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, thicknesses top bottom gate oxide films is derived for asymmetric junctionless double (JLDG) MOSFETs. characteristics between the current voltage by using potential distribution model to propose in this paper. In case, threshold defined as corresponding when (W/L) × 10-7 A, DIBL represent...

<span>This paper studies the impact of fin width channel on temperature and electrical characteristics field-effect transistor (FinFET). The simulation tool multi-gate field effect (MuGFET) has been used to examine FinFET characteristics. Transfer with various temperatures (W<sub>F</sub>=5, 10, 20, 40, 80 nm) are at first simulated in this study. results show that increasing e...