This work describes the design of a double-precision radix-8 divider. Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. The radix-8 divider is compared with one obtained by overlappi...

A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...

A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...

a high accurate and low-voltage analog cmos current divider which operates with a single power supply voltage is designed in 0.18µm cmos standard technology. the proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. the proposed divider is modeled with neural network while tlbo algorithm is used to optimize it. the proposed optimization...

The increasing computation requirements of modern computer applications have stimulated a large interest in developing extremely high-performance floating-point dividers. A variety of division algorithms are available, with SRT being utilized in many computer systems. A careful analysis of SRT divider topologies has demonstrated that a relatively simple divider designed in an aggressive circuit...

A high-speed low power scalable programmable dual modulus digital CMOS frequency divider architecture is proposed. The unique frequency divider architecture includes a high speed parallel counter with State Excitation Module, a switchover trigger circuit, a modulus switchover circuit and a reloader circuit. The mode switchover circuit has two sets of external programmable inputs for two alterna...

Introduction: Fractional-N frequency dividers allow PLL Synthesizers to have frequency resolutions finer than the reference frequency. However, there are two disadvantages in a fractional-N divider, namely, fractional spurs generation and frequency range limitation. A fractional-N divider generates fractional spurs due to the fixed pattern of the dual-modulus divider [1]. The frequency range of...

─ In this paper, the design process of a novel Wilkinson power divider is presented. The proposed power divider features a simple structure with open stubs at each port. With slight changes of the dimensions of open stubs, designed power divider can suppress combinations of each two desired order harmonic simultaneously. From the measured results, 45 dB and 43 dB suppression for 3 and 5 harmoni...

A novel compact ultra-wideband (UWB) in-phase multilayer slotline power divider with high isolation is presented as a complement in slotline power divider field. The new structure proposed in this paper overcomes the shortcoming that power divider based on slotline almost cannot obtain high isolation between output ports. Based on the equivalent-circuit of microstrip-to-slotline transition and ...

A CMOS current divider using a two-variable second-order Taylor series approximation is proposed. The approximation divider is realized with a compact circuit. The simulation results indicate that the approximation divider is feasible for the characteristics of sufficient accuracy, small distortion, and high bandwidth.