The proposed architecture is an all-digital delayand phase-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in analog DLL/PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit ability of DLLs and PLLs to provide fixed timing relationships lets component manu...

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

In this paper we present an ultra low power all digital DLL operating near threshold voltage with lock in range of 80 200MHz. The DLL is immune to false locking problem and dithering around the lock point. Besides clock de-skewing and multiphase clock generation it can multiply the frequency by four. The DLL is implemented in 45nm PTM and operates at 0.7 V and dissipates 120uW at 200MHz. Keywor...

Despite many aspects of the regulation of segmentation being conserved among arthropods, the evolution of novel gene functions has played an important role in the evolution of developmental regulation and the emergence of new segmental structures. Moreover the study of such novel gene functions can be informative with respect to the patterns and direction of evolutionary changes in developmenta...

We demonstrate the fabrication of a tunable-focus dielectric liquid lens (DLL) on a flexible substrate made of polydimethylsiloxane, which was wrapped onto a goggle surface to show its functionality. As a positive meniscus converging lens, the DLL has the focal length variable from 14.2 to 6.3 mm in 1.3 s when the driving voltage increases to 125 Vrms. The resolving power of the DLL is 17.95 li...

The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessar...

In Drosophila, the homeotic gene Distal-less (Dll) has a fundamental role in the establishment of the identity of ventral appendages such as the leg and antenna. This study reports the expression pattern of Dll in the genital disc, the requirement of Dll activity for the development of the terminalia and the activation of Dll by the combined action of the morphogenetic signals Wingless (Wg) and...

The developing legs of Drosophila are subdivided into proximal and distal domains by the activity of the homeodomain proteins Homothorax (Hth) and Distal-less (Dll). The expression domains of Dll and Hth are initially reciprocal. Wingless and Dpp define both domains by activating Dll and by repressing Hth in the distal region of the disc. Wg and Dpp do not act through Dll to repress Hth. Hth fu...

Resolution refinements called weak resolution trees with lemmas (WRTL) and with input lemmas (WRTI) are introduced. Dag-like resolution is equivalent to both WRTL and WRTI when there is no regularity condition. For regular proofs, an exponential separation between regular dag-like resolution and both regular WRTL and regular WRTI is given. It is proved that DLL proof search algorithms that use ...