In this paper a novel methodology to achieve fault tolerance in VLSI Array Processors is proposed. A “Fence” based approach is adopted in which the logic array is partitioned and spares are distributed along the boundary of the active array. The emulator as in conventional fault tolerance techniques takes care of fault mapping and reconfiguration. The latency, reconfiguration interconnect lengt...

In this paper, we present an integrated computeraided design environment, the VAR (VHDL-based Array Reconfiguration) system, for the tasks of design, reconfiguration, simulation, and evaluation in an architecture modeled by VHDL. An easily diagnosable and reconfigurable two-dimensional defect-tolerant PE-switch lattice array is used as an example to illustrate the methodology of VAR. VAR allows...

There are several non-uniform effects on photovoltaic (PV) modules related to aging in a PV array. These subsequently bring about operating parameters with individual modules, causing variance the array performance. The current study undertakes an indoor experimental establish and positively affect efficacy of aged 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="ht...

Received Jan 29, 2017 Revised Mar 29, 2017 Accepted Apr 10, 2017 Recently, research has picked up a fervent pace in the area of fault diagnosis of electrical vehicle. Like failures of a position sensor, a voltage sensor, and current sensors. Three-phase induction motors are the “workhorses” of industry and are the most widely used electrical machines. This paper presents a scheme for Fault Dete...

This paper presents a new technique for construchg a fault-free subarray from a defective WSI (wafer scale integration) processor array based on an integrated diagnosis and reconfiguration (IDAR) method. In a traditional yield enhancement approach, it diagnoses all units first and then the status (faulty or fault-free) of all units are passed to the reconfiguration algorithm for a possible reco...

In this paper, block-level reconfiguration techniques are proposed for content-addressable memories. The CAM words and redundant words are divided into blocks and reconfiguration is performed at the block level instead of the conventional word level. The reconfiguration mechanism used to implement our technique requires negligible hardware overhead. According to simulation results, the hardwar...