A fault-based multifrequency test generation and fault diagnosis procedure is proposed in this work. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis of circuit AC hard/soft faults. The procedure is exempli ed for several self-testable linear analog circuits.

As the complexity of circuit designs grows, designers look toward formal veri cation to achieve better test coverage for validating complex designs. However, this approach is inherently computationally intensive, and hence, only small designs can be veri ed using this method. To achieve better performance, model abstraction is necessary. Model abstraction reduces the number of states necessary ...

We discuss how specification coverage and fault coverage based test derivation strategies can be combined. In particular, the problem of deriving a test suffix, which raises tester confidence in the configuration of the system, reached after a test derived by a specification coverage criterion, is formalized and solved in the CEFSM setting. The traditional mutant-based test derivation approach ...

vision of its delivery of management leader naturally tends to disappear upon the product to the customers, since focus continually shifts to the next test coverage to insure that defective product is not shipped will also be overlookedunderestimated by such managers. Design techniques in the layout that contribute to greater yield will not likely be on their radar screen as their focus will be...

There are multiple scenarios where at-speed coverage over core boundaries is difficult. The idea is to resolve this problem using two stage wrapper. Generally single stage wrapper is used in the present design techniques, and is used in industries. Here two stage wrapper is used in which test coverage has been increased. Additional scan compression architecture is introduced to reduce the patte...

This paper investigates the relationship between multi-cycle false paths and the testability of sequential circuits. We show that removal of multi-cycle false paths (either by circuit restructuring or by proper state encoding) improves circuit testability, but not as signiicantly as one would expect. We demonstrate the inability of current structure-based scan register selection techniques to s...

The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all possible linked faults. The tests are merged into a single test, March SL, detecting all faults in the linked fault space. The preliminary test results of an experiment done at Intel will be reported; they show that Mar...

A recent model for testing systems with multiple timers is extended to compute proper input delays and timeout settings, and is applied to several types of timers required in a testing procedure. In the model, any transition in the specification can be made conditional on a set of running timers. Depending on the path taken to reach an edge, the values of the timer variables may render the trav...

When test vectors are applied to a circuit, the fault coverage increases. The rate of increase, however, could be circuit-dependent. In fact, the actual rise of fault coverage depends on the characteristics of vectors, as well as, on the circuit. The paper shows that the average fault coverage can be computed kom circuit testability. A relationship between fault coverage and circuit testability...