PROOFS (Parallel RestOrative Orderindependent Fault Simulator) is a hybrid of concurrent, differential, and parallel fault simulation algorithms. It retains fault dropping advantage of concurrent method, word level parallelism of parallel method and low memory requirement of differential, while minimizing their individual disadvantages. Parallel simulation of faults reduces simulation time of P...

The aim with this paper is to design a high efficient sequential ATPG on single stack-at fault model. A new approach for sequential circuit test generation is proposed in this paper. With combining the advantage of logic simulation based ATPG and fault simulation based ATPG, higher fault coverage and shorter test sequential length are achieved for benchmark circuit instead of pure logic or faul...

This paper presents an analog fault simulation approach based on concurrent fault detection. By performing fault simulation with fault dropping, high computational effort is saved. The concurrent fault detection can be applied to most analyses and is compatible with other speedupprocedures. Experimental results demonstrate the effectiveness of the presented fault simulation procedure.

this paper presents a new observer design methodology for a time varying actuator fault estimation. a new linear matrix inequality (lmi) design algorithm is developed to tackle the limitations (e.g. equality constraint and robustness problems) of the well known so called fast adaptive fault estimation observer (fafe). the fafe is capable of estimating a wide range of time-varying actuator fault...

This paper proposes a novel Fault Current Limiter (FCL) for the application on distribution networks to control voltage sags at the Point of Common Coupling (PCC) during faults. This new FCL is based on series resonance including resonance transformer and series capacitor. So, by proper design of the series resonance LC tank, the fault current is limited to an acceptable level. The FCL operatio...

In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the ana...

Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, ...

The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation techniqueion. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault c...