We present the design-scheme and physical implementation for a Dynamic Adaptive Neural Network Array (DANNA) based upon the work by Schuman and Birdwell [1,2] and using a programmable array of elements constructed with a Field Programmable Gate Array (FPGA). The aim of this paper is to demonstrate how a single programmable neuromorphic element can be designed to support the primary components o...

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are imple...

Field-Programmable Gate Arrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower NRE cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, Laser-induced MakeLink technology is pr...

This paper presents the design and implementation of a programmable Finite Impulse Response (FIR) Filter using ALTERA Field Programmable Gate Array (FPGA) device. The filter performance is first tested using Filter Design and Analysis (FDA) tool from Mathworks to verify magnitude response and obtain coefficient tables. The test operation includes LPF and BPF filter types with coefficient length...

Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choice, but when using a Field Programmable Gate Array (FPGA), other implementation architectures are possible. This work present a hardware implementation of a broad class of integrate and fire spiking neurons with synapse models u...

The paper focuses on the design and implementation of the base-band basic receiving functions, for a binary CP-FSK demodulator pilot study, as independent modules of a complete Reconfigurable Data-Link (RDL). A model-based approach and Software Defined Radio (SDR) paradigm are used for the design. The implementation will be executed on Field-Programmable Gate Array (FPGA) based hardware.

Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. The solutions implemented on FPGA lead to a high calculation rate using parallelization. We implemented the BCH code in a 3s400FG456 FPGA. In this implementation we used 15 bit-size word code and the results show that the circuits w...