A planar double gate quantum wire transistor (QWT) is proposed and demonstrated. The transistor uses a narrow wire gate placed inside the gap of a split gate to create a single one-dimensional ( 1D) quantum wire (QW) . We demonstrate theoretically and experimentally that the wire gate can create a QW potential with a better confinement and therefore larger subband separations than that in other...

Exclusive-NOR (XNOR) gates are important in digital circuits. This paper proposes the novel design of 2T XNOR gate using pass transistor logic. The proposed circuit utilizes the least number of transistors and no complementary input signal is used. The design has been compared with earlier designed XNOR gates and a significant improvement in silicon area and power-delay product has been obtaine...

Chip scale, high sensitivity magnetic sensor arrays capable of sensing below 100 picoTesla vector fields are of great interest to biomedical applications such as noninvasive medical imaging and diagnosis. Here, we present an integrated magnetoelectric resonant gate transistor (ME RGT) with nanoTesla magnetic field detection sensitivity. The device integrates Titanium (Ti)-Metglas (Fe0.85B0.05Si...

In this paper, the electrical performance of double gate organic field effecttransistor (DG-OFET) are thoroughly investigated and feasibility of the deviceas an efficient biosensor is comprehensively assessed. The introduced deviceprovides better gate control over the channel, yielding better charge injectionproperties from source to channel and providing higher on-state...

A novel method for the reduction of subthreshold slope below the room-temperature Boltzmann limit of 60 mV/dec for a field-effect transistor based on negative differential capacitance is proposed. This effect uses electric field induced electrostriction of a piezoelectric gate barrier of the transistor. The mechanism amplifies the internal surface potential over the applied gate voltage. This i...

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been inve...

The influence of different gate-layout geometries on a cascode nMOSFET’s transit frequencywas studied. Four cascode nMOSFET transistors were fabricated using different interdigitized gate layout geometries. Furthermore, a conventional cascode transistor was fabricated in order to compare it with the proposed interdigitized layouts. The transistors were measured on-wafer and the maximum transit ...

A gate that offers different delays for different input-output paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper,...

Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replaceme...

The floating-gate transistor can be used to design analog circuits, such as current mirrors [1], current scaler[2] and current multiplier [3, 4] and divider [4]. The multiple input floating-gate transistor can be used to design ultra lowvoltage “pseudo differential” pairs [1], hence ULV rail-to-rail amplifiers and analog multipliers are feasible using the floating-gate technique. In this paper ...