Standard cell layouts may need only slight modifications to meet timing constraints. In these situations, general purpose algorithms, which consider numerous parameters of the layout, may be too time consuming or too coarse to make the changes where needed. This paper presents an incremental timing driven placement algorithm designed to “cleanup” a handful of critical paths in a previously plac...

This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introd...

This work explores the effect of adding a simple functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introduced by...

A new incremental approach to placement optimization is proposed in this paper. The approach is based on the sequence pair representation and employs incremental constraint graph computation and incremental longest paths computation. Upper and lower bounds on the average computational complexity are derived and new algorithms are proposed. The average computational complexity of the implemented...

In this chapter, we describe the robust and scalable academic placement tool Capo. Capo uses the min-cut placement paradigm and performs (i) scalable multi-way partitioning , (ii) routable standard-cell placement, (iii) integrated mixed-size placement, (iv) wirelength-driven fixed-outline floorplanning as well as (v) incremental placement.