This paper presents a novel mixed-signal verification methodology for jitter tolerance in highspeed serial-link receiver designs. The predictive approach includes identifying the jitter sources at the receiver input, generating the artificial jitter to add on input data and clock, and investigating the jitter sensitivities inside the receiver with bit error indicator. Both an artificial jitter ...

Version 1, 18 July 2006 This paper discusses the behavioral modeling of a pattern generator including various types of data jitter for jitter tolerance analysis of high-speed serial link receivers during the design phase. The presented model can be used both during the system-level design exploration and the following transistor-level design phases. First, jitter tolerance of clock recovery cir...

Jitter behavior has become increasingly critical design considerations for 12Gbps and 28Gbps transceiver devices featuring stringent specification compliance. In this paper, we present a comprehensive study of noise to jitter transfer mechanism, in which two dominant yet distinct jitter causes, power supply noise and signal crosstalk are investigated by phase noise method. The analysis reveals ...

Phase locked loops for data links operating at 10 Gb/s or faster are low phase noise devices designed to operate with a low jitter reference clock. Characterization of their jitter transfer function is difficult because the intrinsic noise of the device is comparable to the random noise level in the reference clock signal. A linear model is proposed to account for the intrinsic noise of a PLL. ...

Controlled amount of jitter injection into high speed serial bit stream is required for SerDes jitter tolerance test. While jitter injection by Direct Time Synthesis can be a much more cost effective method than a combination of several instruments, it is not widely used yet. Considering its high potential in high volume production test cost reduction, we have studied the basics of the jitter i...

Clock and data recovery (CDR) circuits incorporating bangbang (binary) phase detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and precision required of flipflops and other circuits in the signal path, reducing the complexity and the power dissipation. However, the heavily nonlinear nature of these PDs makes the loop analysis...

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz ...

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking a...

Phase locked loops in 10 Gb/s and faster data links are low phase noise devices. Characterization of their phase jitter transfer functions is difficult because the intrinsic noise of the PLLs is comparable to the phase noise of the reference clock signal. The problem is solved by using a linear model to account for the intrinsic noise. This study also introduces a novel technique for measuring ...