The choice of gate metal technology for junctionless transistors needs to have diverse characteristics as metals distinct work functions and hence, they show incompatibility while tailoring threshold the device. In such a scenario, bimetallic stacked can be promising candidate present wide range tunable required nano-regime transistors. This paper explores electronic phenomena occurring at meta...

The design of double gate n-channel transistor named as junctionless vertical slit field effect transistor (JL VeSFET) is demonstrated in this paper. JLVeSFET is novel twin gate device which turns on and off depending upon the extension of depletion region from two gates inside the channel. It is observed that it offers very low OFF current with ideal subthreshold slope. JLVeSFET is compared wi...

The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthr...

Abstract In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the in transfer characteristics performance of cell owing to WFV. particular, investigate WFV effect, analyzed 2...

In this paper a modified junctionless transistor is proposed. The aim of the novel structure controlling off-current using π-shape silicon window in buried oxide under source and channel regions. changes potential profile region which conduction band energy get away from body Fermi rebuild an electrostatic potential. Beside significant reduced off-current, on current has acceptable value Silico...

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates design of different analog digital using DGJLT. Amplifiers inverters are basic building block electronic ICs. A MOS amplifier converts variation to so...

This paper investigates the effect of gate electrode work function in 30 nm gate length conventional and junctionless FinFETs using technology computer-aided design (TCAD) simulations. DC parameters, threshold voltage (vt), drive current (Ion) and output resistance (Ro), and RF parameters, unity gain cutoff frequency (ft), non-quasi static (NQS) delay and input impedance (Z11) are investigated....