The main idea of this paper is to discuss a new approach to optimize the value of leakage current in MOS transistors. It based on looking for optimal values of the main SPICE parameters which influence the value of the leakage current. These Values make in totally the leakage current, minimal value. The logic and the flow diagrams seem working correctly; various simulation results show the vali...

The proposed estimator consists of a time-domain (TD) index set estimation on the grounds that the leakage outcome followed through a low-complexity TD submit-processing to suppress the leakage. The performance and complexity of the proposed channel estimator are analyzed and established through computer simulation. Simulation outcome exhibit that the proposed estimator outperforms traditional ...

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Le ) of 25 nm ( oxide thickness = 1 1 nm), 50 nm ( oxide thickness = 1 5 nm) and 90 nm ( oxide thickness = 2 5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are ex...

Leakage model plays a very important role in side channel attacks. An accurate leakage model greatly improves the efficiency of attacks. However, how to profile a ”good enough” leakage model, or how to measure the accuracy of a leakage model, is seldom studied. Durvaux et al. proposed leakage certification tests to profile ”good enough” leakage model for unmasked implementations. However, they ...

This paper presents logic level estimators of leakage current for nanoscale digital standard cell circuits. Here the proposed estimation model is based on the characterization of internal node voltages of cells and the characterization of leakage current in a single Field-Effect Transistor (FET). Finally the estimation model allowed direct implementation of supply voltage variation impact on le...