--The All-Digital Phase-Locked Loop (ADPLL) is digital electronic circuit that are used in modern electronic communication systems like frequency synthesizer, modulator/demodulator etc. This paper presents a review of various ADPLL techniques. The range of input frequency of ADPLL is 40 to 98 MHz; the output frequency may be up to 2.92 to 4 GHz range. The components of ADPLL such as phase detec...

Phase locked loop (PLL) is a technique which has contributed significantly toward the technology advancement in communication and motor servo control systems. Inventions in PLL schemes combining with novel integrated circuit have made PLL devices important system components. The development of better modular PLL integrated circuit is continuing. As a result, it is expected that it will contribu...

This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode “log-domain” oscillator in a classical PLL topology to obtain these features. The PLL has been fabric...

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power effic...

A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and temperature variations. A design methodology of such adaptive-bandwidth PLLs and DLLs is described. To assess the impact of each circuit parameter directly, we derive a discrete-time, open-loop dynamic model of ...

the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...

The precision of phase-locked loop (PLL) has a direct effect on the output performance for three-phase grid-connected inverter or three-phase active PFC. In this paper, a new three-phase digital closed-loop phase-locked algorithm is proposed on the basis of synchronous reference frame transformation. Synchronous simulation of the PLL techniques is a good choice even if the polluted three-phase ...

The tracking performance of non-linear amplifier based conventional second order phase locked loop (PLL) and charge pump phase locked loop have been examined numerically by solving the system equations in the presence of lognormal type of fading signal. Some analytical results for non-linear amplifier based conventional phase locked loop and charge pump phase locked loop are also incorporated t...

We proposed a 24-GHz frequency synthesizer (FS) for automotive radar application, which consists of a phaselocked loop (PLL) and an injection-locked frequency multiplier (ILFM). Based on a novel topology, the multiply-by2 ILFM consists of a double-balanced mixer and an injectionlocked oscillator (ILO). The PLL is designed with a 12-GHz voltage-controlled oscillator (VCO) and an injection-locked...

This letter studies frequency-locked rotations in a phaselocked loop (PLL) circuit as FM demodulator. A rotation represents a desynchronized steady state in the PLL circuit and is regarded as another type of self-excited oscillations with natural rotation frequencies. The rotation frequency can be locked at driving frequencies of modulation signals. This letter shows response curves for harmoni...