A method to find hard logic synthesis examples with known upper bound is presented. The circuits can be small and yet difficult to synthesize. Any area-related metric can be used in finding the circuits and testing synthesis tools. The hardness of the examples is robust with respect to the metric used and to minor alterations in the circuit.

In this paper we propose a divide and conquer strategy for the calculation of hazard free prime implicants. It is capable of calculating all hazard free prime implicants but it can be restricted to calculate only those primes that can possibly contribute to a solution. We show that this significantly reduces the number of generated primes, and thus reduces the runtime of the exact minimization ...