In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluatio...

Programmable LUT cascades are used to evaluate multi-output Boolean functions. This paper shows several representations of multi-output functions and introduces a new decomposition algorithm applicable to these representations. The algorithm produces LUT cascades with the limited number of rails, which leads to significantly faster circuits and applicability to large designs. The experiment sho...

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-mm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) mul...

The availability of large, inexpensive memory has made it possible to realize numerical functions, such as the reciprocal, square root, and trigonometric functions, using a lookup table. This is much faster than by software. However, a naive look-up method requires unreasonably large memory. In this paper, we show the use of a look-up table (LUT) cascade to realize a piecewise linear approximat...

The ability to efficiently match completelyspecified logic functions to structures of K-input look-up tables (K-LUTs) is a central problem in FPGA resynthesis algorithms. We address the problem of matching completely-specified logic functions of 9 to 12 inputs in K-LUT structures. Our method is based on the off-line generation of libraries of LUT structures. During resynthesis, matching is perf...

In this paper, we focus on the Look-up Table (LUT) technique for the compensation of HPA nonlinear distortion. An improved LUT method is proposed with better performance compared with conventional LUT technique in terms of convergence speeds, BER and total degradation (TD). It can get over 8 dB gain in out-of-band spectrum re-growth suppression and about 0.3 dB BER performance gain than convent...

Introduction LUT is an acronym for Look Up Table. As LUT techniques become more common for Color correction applications, users are often confused by the multiplicity of available solutions present on the market. Purpose of this document is to present in a simple way the pros and cons of the different techniques and to emphasize on most important features of each solution to help customer decis...

The multiplier uses LUT’s as memory for their computations. The antisymmetric product coding (APC) and odd-multiple-storage (OMS) techniques were proposed for look-up-table (LUT) design. The APC and OMS techniques used for efficient memory-based multiplication. Therefore the combined approach provides a reduction in LUT size to onefourth of the conventional LUT. APC approach is combined with th...

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in faulttolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with selfchecking capabilities. SEDC scheme partitions the contents of ...