Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units. Due to scaling trends and portability of electronic devices there is a high demand and need for low power and high speed digital circuits with small silicon area. So, design and a...

The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power...

Full adder circuit is a basic building block for designing any arithmetic circuits. Due to high demands and need for low and high speed digital circuits with small silicon area scaling trends have increased tremendously. In this paper a new high speed full adder circuit is proposed with very less static and dynamic power dissipation which occupies less silicon area when compared with existing t...

R.ADITHYA ABSTRACT In this paper an ultra low power and probabilistic based noise tolerant latch is proposed based on Markov Random Field (MRF) theory. The absorption laws and H tree logic combination techniques are used to reduce the circuit complexity of MRF noise tolerant latch. The cross coupled latching mechanism is used at the output of the MRF latch inorder to preserve the noise tolerant...

This paper presents a performance analysis of hybrid 1-bit full-adder circuit design. The adder cell is dissected into smaller modules. The modules are analyzed and calculated extensively. To explore good-drivability, noise-robustness, and low-energy operations for deep sub micrometer to explore hybrid-CMOS style design. Hybrid-CMOS design style uses various CMOS logic style circuits to constru...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multipl...

In most of the digital systems the full-adders are the basic and the fundamental components. Due to the increase in number of transistors on the chip and its shrinkage has made the power consumption to be more. This power consumption is due to the flow of current and causes the battery life to be reduced. Hence the need of low power designs is the primary requirement in the VLSI field. The full...

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...

In this paper a new design of full adder cell based on Sense Energy Recovery concept using novel exclusive NOR gates is presented. Low-power consumption and delay are targeted in implementation of our design. The circuit designed is optimized for low power at 0.18-μm and 0.09 μm CMOS process technologies in full custom environment. The new circuit has been compared to the existing work based on...