Introduction In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerged problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastical...

In today’s Integrated Circuits (IC’s) designs Built-in Self Test (BIST) is becoming important for the memory which is the most necessary part of the System on Chip. The March algorithm has been widely used to test memory core of System on chip (SOC). LFSRs and counters are mainly used to generate the memory addresses, which can be serially applied to the memory cores under test. In this paper A...

The trend of cramming more functionality onto a single chip poses alarming problems for testing and diagnosis. Complex chips such as those systems-on-silicon designs usually contain both digital and analog circuitry and include various cores from specialized design houses. Built-In Self-Test is an integrated test solution that could possibly hold down the soaring cost of external ATE machines f...

This paper proposes a simple and effective built-in self-repair (BISR) scheme for content addressable memories (CAMs) with address-input-free writing function. A programmable built-in self-test (BIST) circuit is designed to generate different March-like test algorithms which can cover typical random access memory faults and comparison faults. A reconfigurable priority encoder is proposed to ski...