This project presents two original implementations of improved accuracy current-mode multiplier and divider circuits. Besides the advantage of their simplicity, these original multiplier and divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.9% and 0.75%, respectively, for an extended range of the input c...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

|A voltage controlled di erential injection locked frequency divider (VCDILFD) with a large locking range is designed in a 0:24 m CMOS technology. A 29% locking range is achieved by an optimal inductor design and also by employing high Q accumulation mode MOS varactors to change the free{running oscillation frequency of the divider. The measurement results show frequency division at 5GHz with m...

A CMOS current-mode companding multiplier/divider composed of three compact logarithm circuits and one compact exponential circuit is proposed. Approaches for constructing the logarithm circuits and the exponential circuit are based on second-order Taylor series approximations. By gathering the three logarithm results and passing through the exponential circuit, we can obtain the result of zp(x...

A dual-modulus (divide-by-16/17) prescaler has been designed using a 0.35μm CMOS technology. It consists of a divide-by-4/5 synchronous divider and a divideby-4 asynchronous divider, all implemented with MOS current mode logic. The operating frequency range is simulated to be from 0.8 to 3.1 GHz including all parasitics. The prescaler including the output buffers driving external 50Ω load draws...

Combination of A/D-D/A converters allows implementing multiplier/divider operations. An efficient design based on continuous-time, current-mode, dividing-algorithmic converters is presented in this paper. It offers high speed and capability of low voltage operation, and it is suitable for applications of low or middle resolution (below 9 bits). In addition, the division result is given in both ...

In this paper, we present a broadband out-of-phase power divider with high power-handling capability. The proposed device consists of several sections of double-sided parallel-strip lines (DSPSLs), a mid-inserted conductor plane, and two external isolation resistors, which are directly grounded for heat sinking. A through ground via (TGV), connecting the top and bottom sides of DSPSLs, is emplo...

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-μm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and currentinjection current-mode logic (CICML) divider. A short-pulsed-reset phase fre...