Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regime are investigated. The optimal gate-to-source/drain overlap needed to maximize drive current is found to be different than that needed to minimize FO-4 inverter delay due to parasitic capacitances. It is concluded that the effective channel length must be slightly larger than the physical gate len...

A thorough investigation of N-channel multifinger MOSFET capacitances in dark and under optical illumination is presented in this paper. The intrinsic and extrinsic capacitances are modelled and analysed considering the scaling effects for sub-micron scale MOSFET. Bias dependence is taken into account and capacitances essential for small signal model for RF frequency operation are evaluated. Th...

In mixed circuit simulation, the estimation of parasitic capacitances of deep-submicron MOSFETs is very important. With the continuous scaling of the devices, the extrinsic capacitance, i.e. the overlap and fringing capacitances become a growing fraction of the total gate capacitance. We found the major existing models do not predict correctly the overlap capacitance and the inner fringing capa...

for the purpose of modeling modern VRM, parasitics of VRM must be fully characterized. This paper presents experiment methods to characterize fast switching modern VRM. Results of parasitics, including inductance and resistance, of fast switching VRM are provided. Introduction Modern voltage regulator modules (VRM) for microprocessors have developed to a very high efficiency, very high current ...

A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. T...

Wide-bandgap technology evolution compels the advancement of efficient pulse-width gate-driver devices. Integrated enhanced planar transformers are a source electromagnetic disturbances due to inter-winding capacitances, which serve as route common-mode (CM) currents. This paper will simulate, via ANSYS Q3D Extractor, unforeseen parasitic effects pulse transformer integrated in SiC MOSFET card....

The phenomenal success of CMOS technology, and, then the progress of the information technology, can be attributed without any doubt to the scaling of the MOS transistor, which has been pushed during more than thirty years to increasingly levels of integration and per‐ formances. Then, MOSFETs have been fabricated always smaller, denser, faster and cheaper in order to provide ever more powerful...

The class-E amplifier [1]-[11] is remarked as the next candidate of digital wireless power transmitters. Non-switching power amplifiers suffer from low power-conversion efficiency due to their inherent power loss in high back off area. Hence, switching power amplifiers such as class-D and E are remarked as a remedy for improving power-conversion efficiency and prolonging battery lifetime of por...

This article presents a cascaded gate drive power supply configuration to reduce the common mode (CM) current in phase-shifted full-bridge (PSFB) converters. In such converters, there are at least two $dV/dt$ sources generated different floating points associated parasitic capacitances of isolated barriers drivers (power supplies, and control signal isolation units), which can increase conducte...

There are two dynamics issues in vision chips: (i) The temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. These issues are discussed in [1]–[3] for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances as we...