Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectur...

Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectur...

In behavioral synthesis for resource shared architecture, multiplexers are inserted between registers and functional units as a result of binding if necessary. Multiplexer optimization in binding is important for performance, area and power of a synthesized circuit. In this paper, we propose a binding algorithm to reduce total amount of multiplexer ports. Unlike most of the previous works in wh...

A set of desirable characteristics of a multicarrier spectrumefficient bandwidth-on-demand multiplexer-demultiplexer pair for use in mobile satellite and personal communication systems is identified and described. New characteristics are the use of single VSB channels, design of multiplexer channels based on wavelet packet trees which have specified stopband attenuation, overlap of the multiple...

We focus on non-conflicting construction of an optical multistage feedforward network to emulate the N-to-1 output buffer multiplexer by using switched fiber delay line (SDL). In [1], Y.T. Chen et al. presented a sufficient condition (an upper bound) for the number of delay lines required for such a multiplexer with variable length bursts. In this paper, we first give an improved upper bound. T...

Power dissipation in low powered devices is one of the most important considerations now days. It is very evident that hand held devices such as smart phones, calculators, tablets and laptops etc., which run on battery power, consume very low power for calculations and other operations. In this paper de-multiplexer has been designed using CMOS. In this paper the de-multiplexer has been designed...

A time division multiplexer/demultiplexer for use in an experimental multiple access lightwave network is described. The multiplexer circuit capable of handling data rates up to 100 Mb/sec was built using state of the art emitter coupled logic. This multiplexer is able to absorb a continuous digital data stream at rates between 768 Kb/sec and 100 Mb/sec while at the same time retransmitting the...

www.xilinx.com 1 © 2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. It is obvious that a multiplexer is used to select one of several input signals; however, in this white paper, I will consider a variety of ways in which multiplexers can be...

A multiplexer is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. The low power circuits have become a top priority in modern VLSI design. This paper presents the power consumption comparisons and delay of various designs of 2:1 Multiplexer. The various logic styles such as Differential Cascode Voltage Switch Logic (DCVSL...

Low power and high speed digital circuits are basic needs for any of digital circuit; De-multiplexer is a basic circuit for any digital circuit. In this paper demultiplexer has been designed using CMOS, transmission gate pseudo nmos logic. The performance of designs has been compared in terms of power consumption, delay and transistor counts. The proposed design demonstrates the superiority in ...