Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replaceme...

Noise signals can be equivalently represented in either the frequency domain or the time domain. The representation or modeling in the frequency domain gives the mean square noise current of a transistor as a function of frequency. The representation or modeling of the RTS or l/f noise of nanoscale devices that is easiest to understand is that done in the time domain. The capture and emission o...

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our ...

Alloyed and compound contacts between metal and semiconductor transistor channels enable self-aligned gate processes which play a significant role in transistor scaling. At nanoscale dimensions and for nanowire channels, prior experiments focused on reactions along the channel length, but the early stage of reaction in their cross sections remains unknown. Here, we report on the dynamics of the...

We have simulated the behavior of a rod shaped nanoscale ring-gated field-effect transistor (O-FET) using the PISCES-IIb[1] semiconductor drift-diffusion solver. The results from these simulations are used by a custom SPICE 3f5[2] kernel to simulate several simple logic gates. The usefulness of this kind of transistor is examined within the context of a self-assembling fabrication technique tha...

Semiconductor tetrapods are three-dimensional (3D) branched nanostructures, representing a new class of materials for electrical conduction. We employ the single-electron transistor approach to investigate how charge carriers migrate through single nanoscale branch points of tetrapods. We find that carriers can delocalize across the branches or localize and hop between arms depending on their c...

We have simulated the behavior of a rod shaped nanoscale ring-gated field-effect transistor (RGFET) using the PISCES-IIb[1] semiconductor driftdiffusion solver. The results from these simulations are used by a customized SPICE 3f5[2] kernel to simulate several simple logic gates. The usefulness of this kind of transistor is examined within the context of a selfassembling fabrication technique t...

This study unveils a new tetracene derivative that forms dense, upright monolayers on the surface of aluminum oxide. These monolayers spontaneously self-organize into the active layer in nanoscale field-effect transistor devices when aluminum oxide is used as the dielectric layer. This method gives high yields of working devices that have source-drain distances that are less than 60 nm, thereby...