Network on-chip (NoC) is a novel structural design template, which can be defied for complicated system level on-chip design. NoC has a potential to limit and present the bus-based communication. In this paper, the crisis to discuss is Low power consumption in an Asynchronous Network on-chip (NoC) level communication. NoC is implemented using FPGA which has less fabrication cost and reduces the...

As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network-on-chip (NoC) architectures is the key to h...

A conventional Network-on-Chip (NoC) router uses input buffers to store packets to improve performance, but consume significant power. While bufferless NoC design has shown reduction in area and power, and offers similar performance to conventional buffered designs for many workloads, than conventional buffered routers at high network load. This degradation is a significant problem for widespre...

Network-on-chip (NoC) is deemed to be a paradigm to tackle design challenges in the billion transistor era. A NoC provides a reusable platform for integrating heterogeneous resources. This report discusses application design on NoC. We propose Network-on-Chip Assembler Language (NoC-AL) that serves an interface between NoC implementations and applications, very similar to the instruction set of...

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communicatio...

A new chip design paradigm called Network on Chip (NOC) offers a promising architectural choice for future systems on chips. NOC architectures offer a packet switched communication among functional cores on the chip. NOC architectures also apply concepts from computer networks and organize on-chip communication among cores in layers similar to OSI reference model. We constructed a protomodel us...

Network on Chip (NoC) has been proposed as a good solution to achieve better performance and higher efficiency in today's complex systems on chip. Routing in the NoC is a most important challenge. Final performance of NoC largely depends on the underlying routing scheme. In this paper we evaluate three most efficient routing algorithm namely XY, odd-even and DyAD in 2Dmesh network by different ...

System-on-Chip (SOC) is a microchip consisting of different components such as processor, memory and logic circuitry all on the same chip and for providing communication between these components on the chip Network-on-Chip (NOC) is required as the conventional interconnects are not suitable to fulfil the demands. The application of traditional network technologies in the form of Network-on-Chip...

We discuss why performance verification of systems on chip (SOC) is difficult, by means of an example. We identify four reasons why building SOCs with predictable performance is difficult: unpredictable resource usage, variable resource performance, resource sharing, and interdependent resources. We then introduce the concept of a service, aiming to address these problems, and describe its adva...

Network on Chip (NoC) is a communication paradigm for on-chip communication. It has replaced the traditional bus and crossbar interconnection as it has higher bandwidth, modularity, scalability and benefits of resource reuse. This paper presents the detail survey of the NoC architectures being proposed and implemented in last more than a decade. Apart from comparing the NoC architectures on dif...