We propose an extension to the so-called PD detector. The PD detector jointly monitors received power and correlation profile distortion to detect the presence of GNSS carry-off-type spoofing, jamming, or multipath. We show that classification performance can be significantly improved by replacing the PD detector’s symmetric-difference-based distortion measurement with one based on the post-fit...

* This work was supported, in part, by Texas Instruments Inc., RocketChips Inc. and the R. J. Carver trust. Abstract – The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at highs...

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter•power Figure-Of-Merit (FOM). A sub-sampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noi...

A Phase Locked Loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2Gbit/s-3Gbit/s range ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25u CMOS pr...

Clock recovery circuits which extract the clock signal from random NRZ data are very important to the multigigabit-per-second integrated receivers. Regarding the factors of flexibility and cost of implementation, phase-locked loops are standard approaches to CRCs. In a PLL, the phase detector is a key component which determines several significant properties of the PLL. The goal of this project...

A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at l...

This paper proposes a new partial discharge (PD) pattern recognition method base on the extension theory. First, five types of defect models are well-designed on the base of investigation of many power equipment failures. A commercial PD detector is used to measure the three-dimension (3D) PD patterns, then two fractal features (fractal dimension and lacunarity) and mean discharges of phase win...

Optical detection is reliable in intrinsically characterizing partial discharges (PDs). Because of the great volume and high-level power supply of the optical devices that can satisfy the requirements in photosensitivity, optical PD detection can merely be used in laboratory studies. To promote the practical application of the optical approach in an actual power apparatus, a silicon photomultip...

Partial discharge (PD) behaviors of oil-paper insulation is distinctive in AC and DC combined electric fields in converter transformers from PD behaviors in pure AC or DC electric fields. The present study focuses on the PD developing processes and characteristics of oil-paper insulation systems with needle-plane defects under different AC/DC proportions. The degradation of oil-paper insulation...

--The All-Digital Phase-Locked Loop (ADPLL) is digital electronic circuit that are used in modern electronic communication systems like frequency synthesizer, modulator/demodulator etc. This paper presents a review of various ADPLL techniques. The range of input frequency of ADPLL is 40 to 98 MHz; the output frequency may be up to 2.92 to 4 GHz range. The components of ADPLL such as phase detec...