In this paper, the performance of two low power phase frequency detectors is compared. A modified D-FF based PFD reduces the power consumption of traditional PFD to 4.732uW at 40MHz clock frequency and dead zone to 40ps.It is suitable for low power applications. A Falling Edge PFD uses only 12 transistors. This PFD operates up to 1GHz at 1.8V supply voltage. It consumes only 5.5uW when operatin...

This paper presents a Low power phase frequency detector with charge pump for low power phase lock loop. The phase frequency detector with dead zone compensation has been proposed. The paper contains the detailed circuit diagram of PFD and charge pump with 1.8v power supply and 500MHz input frequency. The design has been realized using 0.18um CMOS technology. Keywords— Low Power, PLL, PFD, CP

Concepts for the generation and the measurement of highly linear frequency ramps are presented. The fractional ramp synthesiser concept shown here is able to generate frequency ramps with a very low phase noise level, a very good frequency linearity and reproducibility. Related to the bandwidth of the generated frequency ramps of 4.5 GHz a relative linearity error below 4·10−10 is demonstrated ...

This paper introduces a new-type Phase-Frequency Detector (PFD) for Charge-Pump based Phase-Looked-loops (CPPLLs). Dead zone in a phase-frequency detector reduces the input detection range and make worse cycle slips. This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the pre-charge time of the internal nodes. With the proposed t...

T his series of articles continues with an analysis of PLL synthesizer design trade-offs. The simple single-loop PLL synthesizer approach exhibits various limitations and trade-offs. Thus, achieving a good performance combination (e.g., small step size and low phase noise) usually requires more sophisticated solutions. The common design trade-offs as well as various methods to improve synthesiz...

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in rang...

This paper presents a novel Phase frequency detector for Charge Pump Phase locked loop (PLL) applications to enable fast frequency acquisition in the phaselocked loop (PLL). To cope with the missing edge problem, the proposed PFD predicts the reset signal and blocks the corresponding input signal during the reset time. The blocked edge is regenerated after the reset signal is deactivated [1]. T...

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in rang...