In this paper, a single precision IEEE 754 floatingpoint multiplier with high speed and low power is presented. The bottleneck of any single precision floating-point multiplier design is the 24x24 bit integer multiplier. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 24x24 bit multiplication operation is...

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical path...

Multiplying floating point numbers is a critical requirement for DSP applications involving large dynamic range. This paper focuses only on single precision normalized binary interchange format targeted for Xilinx Spartan-3 FPGA based on VHDL. The multiplier was verified against Xilinx floating point multiplier core. It handles the overflow and underflow cases. Rounding is not implemented to gi...

Interval arithmetic provides an e cient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are often too slow for numerically intensive computations. This paper presents the design of a multiplier that performs either interval or oating point multiplication. This multiplier requires only slightly more area and dela...

High speed execution of arithmetic operations and high degree of precision in real time system are of major concern in any digital signal processing (DSP). Speed of DSP depends on speed of multiplier and algorithm used. In this paper we propose Residue Number System method for fast “carry free” floating point arithmetic operations. Floating Point RNS units have obvious advantages over tradition...

We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost ...

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Quadruple, double, and single precision floating point multipliers are implemented using conventional, Canonical Signed Digit (CSD), Vedic, and radix-4 Booth multiplier methods using Verilog language and ...

In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier design is the 53x53 multiplication of the mantissas (52 bit mantissa+1 hidden bit). This paper proposes a approach to improve this performance bottleneck by adding a redundant 54 bit initialized to ‘0’ in the mantissas o...

In order to meet the requirements in real time DSP applications MAC unit is required. The speed of the MAC unit determines the overall performance of the system. MAC unit basically consists of Multiplier, adder and an accumulator unit. In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format. In this research work MAC uni...