In this paper, we present a performance comparison of existing clocked dynamic comparators. As delay is directly correlated with the submicron scaling, we investigate the performance of the above comparators in terms of delay and Power-Delay Product (PDP). PDP gives the average energy dissipated by the comparator for a single comparison. Simulation results using Mentor Graphics revealed better ...

In this paper, a novel implementation of 8x8 Multiplier using 4-2 Compressors is presented; which produces quick results, especially for use in Digital Signal Processors and in Microprocessors. This multiplier uses a new partial-product reduction format which consecutively reduces the maximum output delay. The new design of multiplier requires less number of MOSFET’s compared to Wallace Tree Mu...

The overall view of this paper is to attain high speed, low power full adder cells with alternative logic cells that lead to have reduced power delay product. Two high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-add...

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84 V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improveme...

Motivations of CMOS technology scaling are higher speed of operation, benefit of integration density and lower power dissipation. CMOS technology has crossed many hurdles over the past four decades. The aggressive technology scaling is causing device parameter variations, which is more severe than earlier. This paper carries out variability analysis of various popular exclusive-OR circuits at t...

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substr...

ARTICLE INFO In digital signal processing we use delayed least mean square adaptive filter is used to find the lower adaptation delay and area –delay-power efficient architecture which uses the novel partial product generator. The proposed system optimizes the balanced pipelining across the time consuming combinational blocks of the structure. The objective is to reduce the number of pipelining...

In this paper, we present an efficient architecture for the implementation of a delayed least mean square Adaptive filter. For achieving lower adaptation-delay and area-delay-power, we use a novel partial product generator and propose an optimized balanced pipelining across the time-consuming combinational blocks of the structure.We propose an efficient fixed-point implementation scheme in the ...

Multiple Valued Logic (MVL) has some important benefits such as increased data density, increased computational ability, reduced dynamic power dissipation Therefore with the help of Multiple Valued Logic (MVL) we have designed two quaternary multiplier architecture. The partial products in the multiplier are designed with quaternary voltage mode circuits. Each multiplier architecture is designe...

– A novel circuit topology for the CMOS based Incrementer/Decrementer circuit is presented in this paper. The design methodology is extensively based on Domino logic and it utilizes a simple two level look-ahead structure. The highly parallel, regular structure of the proposed 8-bit decision module (DM) macro cell makes this design, especially advantageous for constructing higher order versions...