A power efficient gain adjustment technique is described to realize programmable gain current mirror. The dissipation power changes over the wide gain range of structure are almost negligible. This property is in fact very interesting from power management perspective, especially in analog designs. The simple structure and constant frequency bandwidth are other ever-interesting merits of propos...

In present VLSI technology energy dissipation is an important factor to be considered among other factors like area, speed and performance in portable devices. The size reduction and complexity of portable devices have resulted in large amount of power dissipation in the devices. As a result low power designs have become inevitable part of today’s devices. In this paper low power dissipation is...

Previous research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test effi...

Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can...

Dynamic Power by internal capacitance * Short-circuit Current Dissipation . ~ ~ ~ ~ ~ i ~ i ~ ~ i~~ 1 I Delay Abstract---It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate, which has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which...

This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty. We derive closed form optimal solutions for both cases. These closed form solu...

The first challenge, power dissipation, became evident at the beginning of this decade, and the importance has only grown in magnitude in the last several years. Power dissipation manifests as a problem in three fundamental ways: 1) high power dissipation is the primary performance limiter for mainstream highperformance microprocessors — it is simply not cost-effective to cool and deliver power...

As a method for greatly reducing power dissipation in logic networks, we propose some logic organization techniques for logic networks. By such techniques, their power dissipation is to be minimized under certain input conditions, or the average power dissipation in the whole network should be minimized. A logic network in which these problems are taken into account will be called a power minim...

This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimising short circuit power and subthreshold leakage power which is predominant when

Low power consuming devices are playing a dominant role in the present day VLSI design technology. If the power consumption is less, then the amount of power dissipation is also less. The power dissipation of a device can be reduced by using different low power techniques. In the present paper the performance of 4x1 multiplexer in different low power techniques was analyzed and its power dissip...