In this paper, a method for the systematic generation of the executing programs for the processor element of the parallel ASIC or FPGA-based systems liked to processor arrays is proposed. In this method, the each processor element of the array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. Thi...

Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today , a reconfigurable device can integrate a large-scale processor and complex hard-wired logic. System designers found that they need a high-performance processor for their reconfigurable device based systems. To improve processor performance , a multithreade...

This paper presents a novel compiler algorithm for selecting program slices that prefetch load values concurrently with program execution. The algorithm is evaluated in the context of an intelligent memory system. The architecture consists of a main processor and a simple memory processor. The intelligent memory system pre-executes program slices and forwards values of critical loads to the mai...

This paper presents the effectiveness of an interactive support facility to tune processor allocation of data-driven realtime programs on CUE (Coordinating Users’ requirements and Engineering constraints)-series super-integrated dynamic datadriven processors. In tuning processor allocation of data-driven programs on CUE processors, one of the most critical issues is how to detect and remove sid...

Look-ahead dynamic inter-processor connection reconfiguration is a multi-processor architectural model, which has been proposed to eliminate connection reconfiguration time overheads. It consists in preparing link connections in advance in parallel with program execution. An application program is partitioned into sections, which are executed using redundant communication resources. Parallel pr...

The problems of multiprocessor partitioning and program allocation are interdependent and critical to the performance of multiprocessor systems Minimizing resource partitions for parallel programs on partitionable multiprocessors facilitates greater processor utilization and throughput The pro cessing resource requirements of parallel programs vary during program execution and are allocation de...

Architectural simulators used for microprocessor design study and optimization can require large amount computational time and/or resources. In such cases, models can be a fast alternative to lengthy simulations, and can help reach a designer near-optimal system configuration. However, The nonlinear characteristics of a processor system make the modeling task quite challenging. The models not o...