Multiple Valued Logic (MVL) has some important benefits such as increased data density, increased computational ability, reduced dynamic power dissipation Therefore with the help of Multiple Valued Logic (MVL) we have designed two quaternary multiplier architecture. The partial products in the multiplier are designed with quaternary voltage mode circuits. Each multiplier architecture is designe...

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achie...

Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary...

Multiple-valued logic (MVL) application in the design of digital devices opens additional opportunities. In this paper we have designed Quaternary latch & quaternary multiplexer. Multiplexer is designed with different threshold voltages. All the circuits were simulated with the Spice tool using TSMC 250 nm technology and have shown improvements in performance and power consumption and propagati...

-In binary number system carry is a major problem in arithmetical operation. We have to suffer O(n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry free arithmetical operation. Further, literature reviews suggest that multi-valued logic (MVL) would be a better choice to address the problem of developing faster chips for performing f...

The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We emulated many benchmark circuits on PBM128, and compared its memory size and computation time with the Intel’s Core...