The design of a FIFO buffer supporting synchronisation-free, non-blocking, reading and writing operations is presented. The circuit consists of a standard self-timed FIFO surrounded by two interface blocks, In and Out, which together provide temporal independence between the reader and writer processes. These blocks are synthesised from their Signal Transition Graph (STG) specifications using a...

Equivalence relations between closed tandem queueing networks are established. Four types of models are under consideration: single-server infinite-capacity buffer queues, infinite-server queues with resequencing, single-server unit-capacity buffer queues with blocking before service, and single-server unit-capacity buffer queues with blocking after service. Using a customer/server duality we s...

Field-Effect Passivation The implementation of Ga2O3 thin film effectively passivates the CZTS/TiO2 heterojunction by blocking holes away from buffer layer and acts as an electron-selective contact. This hole-blocking reduces interface recombination evident significant photoluminescence quenching. More information can be found in article number 2200001 Mukesh Kumar co-workers.

A buffer-aware worst-case timing analysis of wormhole NoC is proposed in this paper to integrate the impact of buffer size on the different dependencies relationship between flows, i.e. direct and indirect blocking flows, and consequently the timing performance. First, more accurate definitions of direct and indirect blocking flows sets have been introduced to take into account the buffer size ...

In the current Internet, many HTTP sessions are established between Web clients and servers via Web proxy servers. Since the Web proxy server accommodates lots of TCP connections from Web client hosts, and those to Web servers, it cannot show sufficient performance if the resources of the proxy server should be utilized effectively. In this paper, we propose a new resource management scheme for...

It is generally accepted that optimal TCP receive buffer size is based on network conditions. We argue that processing limitations at the end hosts should also be a consideration. We present initial analysis as to the validity of this argument, noting process-receive buffer dynamics and its affect on throughput. Based on our observations, we offer suggestions as to how better network performanc...

Writing data to a page not present in the file-system page cache causes the operating system to synchronously fetch the page into memory first. Synchronous page fetch defines both policy (when) and mechanism (how), and always blocks the writing process. Non-blocking writes eliminate such blocking by buffering the written data elsewhere in memory and unblocking the writing process immediately. S...

Current message-passing parallel computers provide send and receive primitives with a wide variety of blocking, synchronization , selectivity and ordering properties. Unfortunately , the interactions between the diierent properties of the send and receive primitives can be extremely complex, and as a result, the precise semantics of these primitives are not well understood. In this paper we pre...

Banyan networks are being proposed for interconnecting memory and processor modules in multiprocessor systems as well as for packet switching in communication networks. This paper describes an analysis of the performance of a packet switch based on a single-buffered Banyan network. A model of a single-buffered Banyan network provides results on the throughput, delay, and internal blocking. Resu...