The paper analyses different techniques that might be employed in order to solve various problems of combinatorial optimization and argues that the best results can be achieved by the use of software, running on a general-purpose computer, together with an FPGAbased reconfigurable co-processor. It suggests architecture of combinatorial co-processor, which is based on hardware templates and cons...

System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become increasingly important in defining architecture tradeoffs. While technology improvements enable increasingly complex processor implementations, there are physical and program behavior limits to the usefulness of this comp...

Amalgam is a novel architecture for multifunction embedded systems. It integrates multiple reconfigurable and programmable processing resources (known as clusters) to achieve high-performance with low design effort on a variety of multimedia applications. The reconfigurable cluster (RClust) enables Amalgam to exploit the natural parallelism and operator granularities of a target application. Th...

Binary image processing is a powerful tool in many image and video applications. This paper describes A reconfigurable processor for binary image processing. Reconfigurable binary image processing chips have been designed mainly for the binary image applications of a chip. The processor architecture is designed for input output control unit, reconfigurable binary processing module, and peripher...

In this paper, we develop a heterogeneous architecture for the reconfigurable functional unit of an extensible processor. To verify the efficiency of our architecture, we applied it to 8 applications of Mibench. The new architecture improves execution time of custom instructions by 20% to 30% on average while supporting more custom instructions. The area and the total wire length are reduced by...

The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to be solved before any practical general-purpose reconfigurable system is built. One fundamental problem is the placement of the modules on the reconfigurable functional unit (RFU). In reco...

This paper addresses the design of a Reprogrammable Combinatorial Processor (RCP) on the basis of reconfigurable circuits such as FPGA. The RCP is intended to be used for solving different combinatorial problems formulated over discrete matrices. From a structural point of view the RCP is a composition of a Reconfigurable Control Unit (RCU) and a Reconfigurable Function Unit (RFU). Each unit co...

In this paper we describe a peer-to-peer interface between processor cores and reconfigurable fabrics. The main advantage of the peer-to-peer model is that it greatly expands the scope of application for reconfigurable computing and hence its potential benefits. The primary extension in our model is that “code” on the reconfigurable hardware unit is allowed to invoke routines both on the reconf...

In this paper, we investigate the implementation of reconfigurable computing in commercial applications. A Reconfigurable Processing Unit, the Xilinx XC6200 is introduced and our design flow with the HOTWorks development system is shown. We show the design of reconfigurable computing versions of Photoshop plug-ins, and compare various approaches of implementation. We analyze the test result and...

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfigura...