The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discha...

A self-cascading CMOS circuit for operation in weak inversion is presented. The self-cascoding MOSFET circuit has been shown to exhibit greater than twentY:'fold increase in the output resistance, without paying virtually any penalty in real estate and power consumption. The circuit has been used to increase the gain in the front stage of operational amplifiers, and to obtain improved performan...

This paper presents a high performance switched current memory cell The cell is designed for reduced supply voltages and low power For audio applications an accuracy around bits is mandatory The accuracy of the basic memory cell su ers from channel modulation and clock feedthrough errors The channel length modulation error is reduced by cascoding the memory transistor The high gain of the casco...

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with conventional global-feedback technique, proposed TIA has advantages of wider bandwidth, and lower power dissipation. The schematic characteristics circuit are described. Moreover, employs inductive peaking to increase bandwidth. is implemented using 65 nm complemen...

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hy...

The influence of different gate-layout geometries on a cascode nMOSFET’s transit frequencywas studied. Four cascode nMOSFET transistors were fabricated using different interdigitized gate layout geometries. Furthermore, a conventional cascode transistor was fabricated in order to compare it with the proposed interdigitized layouts. The transistors were measured on-wafer and the maximum transit ...