This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hy...

This work presents the design of an inductively source degenerated CMOS differential common source cascode Low Noise Amplifier (LNA) operating at 2 GHz frequency. An inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. Another inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically com...

In this paper we report the fabrication, design and testing of an uncooled infrared imager based on an active pixel heat balancing technique. The imager is fabricated using a commercial CMOS process plus a simple electrochemical etch stop releasing step. The basic active pixel detector structure consists of a simple cascode CMOS amplifier in which the PMOS devices are built inside a thermally-i...

The influence of different gate-layout geometries on a cascode nMOSFET’s transit frequencywas studied. Four cascode nMOSFET transistors were fabricated using different interdigitized gate layout geometries. Furthermore, a conventional cascode transistor was fabricated in order to compare it with the proposed interdigitized layouts. The transistors were measured on-wafer and the maximum transit ...

To proof low voltage techniques are valid in current conveyor design, Bulk driven and composite transistor (self cascode) techniques are used to get high performance results from CCII in low voltage supply. Conventional operational amplifier circuit from literature was our choice as core of the design. Our Focus with using low voltage techniques is study the frequency characteristics of a CCII ...

After explaining the basic operation of a SiC JFET plus silicon MOSFET cascode circuit, the dynamics of cascode switching will be discussed and the use of a QRR tester to evaluate the reverse-recovery characteristics of a cascode circuit will be explained. A comparison of the cascode’s reverse recovery with that of a SiC MOSFET reveals that the JFET cascode actually performs better than the SiC...

in this study an ultra-broad band, low-power, and high-gain cmos distributed amplifier (cmos-da) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. it is created bycascading of inductively coupled common-source (cs) stage and regulated cascode configuration (rgc).the proposed three-stage da is simulated in 0.13 μm cmos process. it achieves flat and high ...

AbstractThis paper deals with the design and analysis of folded cascode operational transconductance amplifier in different regions of operations: strong, weak and moderate inversion region. The folded cascode OTA consists of cascode OTA and cascode gain boosting technique. By using 0.35μm technology, the simulation shows DC gain of 78.42dB with a unity gain bandwidth of 446.07 MHz and power co...