PROOFS (Parallel RestOrative Orderindependent Fault Simulator) is a hybrid of concurrent, differential, and parallel fault simulation algorithms. It retains fault dropping advantage of concurrent method, word level parallelism of parallel method and low memory requirement of differential, while minimizing their individual disadvantages. Parallel simulation of faults reduces simulation time of P...

This paper addresses the analysis of combinational cycles in synchronous, sequential circuits. A circuit that has a com-binational cycle does not necessarily have unstable output behavior: the cycle may be \false" for all reachable states and possible input sequences, or the unstable behavior on the cycle may not aaect the outputs. We provide a procedure to determine whether a circuit produces ...

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. An LUT ring consists of memories, a programmable interconnection network, a feed-back register, an output register, and a control circuit. It sequentially emulates an LUT cascade that represents the state transition functions and the output functions. We present two algorithms for synthesizing a seque...

With the growth in complexity of VLSI circuits, test generation for sequential circuits is becoming increasingly diicult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more eeective and powerful sequential test generators. In this paper we describe and illustra...

The sequential circuit state space diameter problem is an important problem in sequential verification. Bounded model checking is complete if the state space diameter of the system is known. By unrolling the transition relation, the sequential circuit state space diameter problem can be formulated as an evaluation for satisfiability of a Quantified Boolean Formula (QBF). This has prompted resea...

Static verification techniques leverage Boolean formula satisfiability solvers such as SAT and SMT solvers that operate on conjunctive normal form and first order logic formulae, respectively, to validate programs. They force bounds on variable ranges and execution time and translate the program and its specifications into a Boolean formula. They are limited to programs of relatively low comple...