This paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-co...

With the growth in complexity of VLSI circuits, test generation for sequential circuits is becoming increasingly diicult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more eeective and powerful sequential test generators. In this paper we describe and illustra...

An asynchronous unit delay is an n input n output of the input n-tuple prior to the last inlput change. It asynchronous sequential circuit in which the present value of the will then be shown that every asynchronous definite flow output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining ablecan brizeday a fee bac r ...

The paper deals with synthesis of sequential circuits defined by their algorithmic state machine notation. Such circuits have a number of specific properties which enable efficient design of the circuits by utilizing so-called linearization techniques. A typical linearization technique includes calculation of autocorrelation values for a system of logic functions corresponding to the circuit. F...

This paper states the necessary and sufficient conditions for the existence of a feedforward inverse for a feedforward linear sequential circuit and gives an implicit procedure for constructing such inverses. It then goes on to give the necessary and sufficient conditions for the existence of general inverses with finite delay and gives procedures for constructing a class of such inverses. The ...

In this paper, we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. The BDDbased approaches for equivalence checking can easily run into memory explosion for such designs. With an attempt to hand...

TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity...