On-board Error Detection and Correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer and its local memory. This paper presents a comparison of the performance of four low complexity EDAC techniques for application in Random Access Memories (RAMs) on-board small satellites. The performance of a newly proposed EDAC archite...

SEU error rates in the CMS tracker environment have been approximated with Monte Carlo simulations. The estimated upset rates for a submicron technology are 8.3 10-7 upsets/(bit s) at 4.9cm and 1.1 10-8 upsets/(bit s) at 49cm from the beam line, respectively. Comparison of simulation data with experimental proton irradiation benchmarks points to a tenfold underestimate of the actual rate. All t...

A high speed 15 ns 4 Mbits asynchronous SRAM, 500 Astand-by current, 300 Krads total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allo...

The effect of technology scaling (0.5–0.09 m) on single event upset (SEU) phenomena is investigated using full two-dimensional device simulation. The SEU reliability parameters, such as critical charge ( crit), feedback time ( fd) and linear energy transfer (LET), are estimated. For 0 18 m, the source node collects a significant fraction of radiation-induced charge resulting in an increase of L...

This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...

This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) o...

Orbital remote sensing instruments and systems benefit from high performance, adaptable computing systems. Field programmable SRAM-based gate arrays (FPGAs) are usually the chosen platform for real-time reconfigurable computing. This technology is driven by the commercial sector, so devices intended for the space environment must be adapted from commercial product. Total ionizing dose, heavy io...

SRAM based FPGAs are attracting considerable interest especially in aerospace applications due to their high reconfigurability, low cost and availability. However, these devices are strongly susceptible to space radiation effects which are able to cause unwanted single event upsets (SEUs) in the configuration memory. In order to mitigate the SEU effects, various methods have been investigated i...

-This paper discuss about the method for designing error tolerant systems in SRAM-based FPGAs. SRAM-based FPGAs are preferred in mission based critical space applications. But due to high radiation on the sensitive part of the circuits which introduces errors called Single Event Upset (SEU).Sometimes these types of errors results the permanent malfunction of the entire system. Different error d...

This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsign...