Introduction In recent years, the noise performance of CMOS image sensors has improved significantly with the implementation of a multiple sampling architecture [1-3]. In the multiple sampling architecture, the thermal noise of the pixel source follower can be reduced by a factor equal to the square root of the sampling number. The multiple sampling architectures usually employ single slope (SS...

This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with pinned-photodiode as detector. The test sensor has been fabricated in 0.18 μm CMOS image sensor process from TSMC. The ADC nonlinearity measurement result shows tota...

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the ref...

iii I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. ________________________________ (Mark Horowitz) Principal Adviser I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor o...

This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active elemen...

ACKNOWLEDGMENTS Since I left my country to study abroad, two years almost passed. I spend the first year at Delft, the Netherlands, for the courses studying. The second year I moved to Leuven, Belgium, for my master thesis. I had a happy life in the past two years, even though it was full of challenges. Here I would like to acknowledge a lot of people, who accompanied me and shared my happiness...

An 80MS/s analog-to-digital converter (ADC) based on single-slope conversion is presented which utilizes a recently developed gated ring oscillator (GRO) time-to-digital converter (TDC) to achieve an ENOB of 6.45 bits. To save power, the time-to-digital conversion is done in two steps, the first of which is based on coarse time quantization as measured by cycles of an oscillator and the second ...

This paper proposes a column-wise two-step SingleSlope (SS) ADC, which improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high-speed CIS. To remove the problem of missing code in multi-stage structures, occurring on every boundary between steps of the coarse ADC, the range of the fine ADC is doubled to cover the boundary. The sampling rate of the ADC is...