Here we study the discrete lot-sizing problem with an initial stock variable and an associated variable upper bound constraint. This problem is of interest in its own right, and is also a natural relaxation of the constant capacity lot-sizing problem with upper bounds and fixed charges on the stock variables. We show that the convex hull of solutions of the discrete lot-sizing problem is obtain...

Here we study the discrete lot-sizing problem with an initial stock variable and an associated variable upper bound constraint. This problem is of interest in its own right, and is also a natural relaxation of the constant capacity lot-sizing problem with upper bounds and fixed charges on the stock variables. We show that the convex hull of solutions of the discrete lot-sizing problem is obtain...

[1] corresponding author e-mail: [email protected]   [1] corresponding author e-mail: [email protected]   lot-sizing problems (lsps) belong to the class of production planning problems in which the availability quantities of the production plan are always considered as a decision variable. this paper aims at developing a new mathematical model for the multi-level capacitated lsp w...

Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of signi cant...

In this paper we investigate the complexity of the economic lot-sizing problem with remanufacturing (ELSR) options. Whereas in the classical economic lot-sizing problem demand can only be satisfied by production, in the ELSR problem demand can also be satisfied by remanufacturing returned items. Although the ELSR problem can be solved efficiently for some special cases, we show that the problem...

In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By ...

We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suit...

We address the problem of generating mesh sizing functions from a set of points with specified sizing values. The sizing functions are shown to be maximal and K-Lipschitz, with arbitrary parameter K provided by the user. These properties allow generating low complexity meshes with adjustable gradation. After constructing an additively weighted Voronoi diagram, our algorithm provides fast and ac...