This paper demonstrates a feedforward active substrate noise cancelling technique using a power supply di/dt detector. Since the substrate is usually tied with the ground line with a low impedance, the substrate noise is closely related to the ground bounce which is proportional to the di/dt when inductance is dominant on the ground line impedance. Our active cancelling detects the di/dt of the...

Substrate noise generated by digital circuits on mixed-signal ICs can disturb the sensitive analog/RF circuits, such as Low Noise Amplifier (LNA), sharing the same substrate. This paper investigates the adverse impact of the substrate noise on a high frequency cascode LNA laid out on a lightly doped substrate. By studying the major noise coupling mechanisms, a new and efficient modeling method ...

Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-lockedloops are widely used as clock generators of microprocessors. Although exploiting advanced circuit techniques reduces the timing jitter induced by the ...

Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. To simulate this performance degradation, the total amount of substrate noise must be known. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator due to the long simulation times and high memory requirements. We are...

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is ...

Noise Coupling in Heavily and Lightly Doped Substrate from Planar Spiral Inductor Tony Yeung, Alan Pun, Zhiheng Chen, Jack Lau, Fran cois J.R. Cl ement Dept. of Electrical & Electronic Engineering, The Hong Kong University of Science & Technology Center for Integrated Systems, Stanford University, Stanford, CA 94305 Abstract| Recently, much studies have been done to include on-chip inductors fo...

This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed i...

Mixed-signal circuit design has historically been a challenge for several reasons. Parasitic interactions between analog and digital systems on a single die are one such challenge. Switching transients induced by digital circuits inject noise into the common substrate creating substrate noise. Analog circuits lack the large noise margins of digital circuits, thus making them susceptible to subs...

In this paper we address the main problems posed by substrate noise from two complementary points of view. We look at the effects of substrate noise on performance and reliability in digital, analog and mixedsignal circuits. The mechanisms underlying noise generation, injection, and transport are also analyzed. Solutions to the substrate noise problem using design and layout techniques, as well...

Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equi...