Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60mV/decade subthreshold swing and very small OFF current (IOFF), its practical application is questionable due to low ON current (ION) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60mV/decade subthreshold swi...

We present an analytical model for the subthreshold characteristic of ultra-thin Independent Double-Gate transistors working in the ballistic regime. This model takes into account short-channel effects, quantization effects and source-to-drain tunneling (WKB approximation) in the expression of the subthreshold drain current. Important device parameters, such as off-state current or subthreshold...

733 Abstract— This paper has studied subthreshold characteristics for double gate(DG) MOSFET using Gaussian function in solving Poisson's equation. Typical two dimensional analytical transport models have been presented for symmetrical Double Gate MOSFETs (DGMOSFETs). Subthreshold swing and threshold voltage are very important factors for digital devices because of determination of ON and OFF. ...

We report the electrical and optical properties of ZnO/ZnS core/shell nanowire (NW) devices. The spatial separation of charge carriers due to their type II band structure together with passivation effect on ZnO/ZnS core/shell NWs not only enhanced their charge carrier transport characteristics by confining the electrons and reducing surface states in the ZnO channel but also increased the photo...

Introduction: Current-mode logic (CML) circuits are widely used in many high-speed and high-performance applications [1]. The differential topology of CML circuits provides high immunity to supply noise and crosstalk, while reduced voltage swing at the output helps to operate the circuit in very high frequencies with low noise generation [1, 2]. These properties make the MOS CML (MCML) topology...

We present a novel n-type InGaAs quantum-well metal–oxide–semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III–V MOSFETs. The device structure features a composite InP/ Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have ...

• Ab initio simulation of Nanowire at cryogenic temperature. Robust ab simulation. Subthreshold slope nanowire with gate length = 10 nm. In this paper, we propose a methodology for robust and accurate ab-initio quantum transport down to 3 K an n -type Si nanowire. This is important understand the subthreshold swing (SS) We show that L G nm, SS fully dominated by direct tunneling temperature, wh...

This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconductance efficiency and low gate bias condition. The top resistive biasing has more benefit with the feature of phase noise than MOS current source since it can support the low-noise c...