This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different s...

The spirit of system-on-chip (SoC) approach is to integrate more and more system functions into one single chip. Consequently, the on-chip clock requirement could be very complicated due to the various functions the chip has to support. To fulfill those clock needs, it is not uncommon for more than several phase-locked loop (PLLs) to be used within one such large chip. Designing these on-chip P...

Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level ...

As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip. Starting with a broad idea of test problems, this survey paper focus on “Chip” Built in Self-Test (BIST) study and its promotion for board and system-level applications. This paper gives brief informative review of Built-in Self-test (BIST) and its testing techniques. Recently B...

This paper presents a novel intellectual-property (IP) identification scheme using the existing System-on-a-Chip (SOC) watermarking design. An efficient and novel principle is established for IP identification which depends on the current IP design flow. The principle is embedding different Advanced Encryption Standard (AES) encoders in to System-on-a-Chip (SOC) based watermarked devices at beh...

System-on-Chip (SoC) on chip communication architecture solved the problem of how to interconnect hundreds of processing element (PE) and storage element (SE) inside one chip, but in the other hand it introduced power consumption hindrance in the communication elements such as bridges, bus wire, bus interface and arbiters to the overall power usage in the chip. Various power estimation techniqu...

Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. For these SoC platforms, multicast communication is significantly used for parallel applications. Cache coherency in distributed ...

The Architecture for a multi-technology testbench on a chip is presented for functional testing of mixed signal devices. The technologies tested by this System-on-a-Chip (SoC) include Op Amps, biosensors, and smart signal processing of Analog/Digital Multiplexers. This paper focuses on describing the architecture of the testbench on a chip as well as the results obtained from testing integral c...

The Soc (system on a chip) is a new form of embedded system, which integrates microprocessor, analog IP cores, digital IP core and memory (or off-chip memory controller interface) on a single chip. It is usually customized (CSIC) or a standard product for particular purposes (ASSP). It successfully integrate the hardware integrated circuits and embedded software, which can implement the compute...