Extending the projection method for the synthesis of systolic arrays , we present a procedure for the design of xed-size systolic arrays using a technique called "locally sequential globally parallel" (LSGP) partitioning. Our main result, which gives a necessary and suucient condition to characterize the boxes in which cells can be merged without connict, is the key to the procedure presented h...

Efficient encoding algorithms are presented for two types of constraints on two-dimensional binary arrays. The first constraint considered is that of t-conservative arrays, where each row and each column has at least t transitions of the form ‘0’ !‘1’ or ‘1’ ! ‘0.’ The second constraint is that of two-dimensional DC-free arrays, where in each row and each column the number of ‘0’s equals the nu...

For all systolic groups we construct boundaries which are EZ–structures. This implies the Novikov conjecture for torsion–free systolic groups. The boundary is constructed via a system of distinguished geodesics in a systolic complex, which we prove to have coarsely similar properties to geodesics in CAT (0) spaces. MSC: 20F65; 20F67; 20F69;

By studying connectedness at infinity of systolic groups we distinguish them from some other classes of groups, in particular from the fundamental groups of manifolds covered by euclidean space of dimension at least three. We also study semistability at infinity for some systolic groups.

In this article we present a model of coarse grained reconfigurable architecture, dedicated to accelerate data-flow oriented applications. The proliferation of new academic and industrial architectures implies a large variety of solutions for platform-based designers. Thus, efficient metrics to compare and qualify these architectures are more and more necessary. Several metrics, Troughput Densi...

We present an overview of a prototype system based on a functional language for developing regular array circuits. The features of a simulator, oorplanner and expression transformer are discussed and illustrated.

The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm expressed in C source code is progressivly re-written into a recurrence form from which systolic structures can be deduced. The paper extends previous work by the authors by introducing a simplification to a previous syst...