adder carry-lookahead, 131–133 full, 110, 129 half, 147 modulo-p, 524 ripple-carry, 130 serial-binary, 266–268 ternary, 148 admissible pattern, 189 algebraic divisor, 156, 234 double-cube, 234 multiple-cube, 234 single-cube, 234 algebraic factorization, 234–236, 247–250 targeted, 248 algebraic resubstitution, 234 aliasing, 463 alphabet code, 504–506 input, 270, 313, 414, 432, 441 output, 271, 4...

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrates several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results ar...

We have constructed a solution-phase array of three deoxyribozyme-based logic gates that behaves as a half-adder. Two deoxyribozymes mimic i(1)ANDNOTi(2) and i(2)ANDNOTi(1) gates that cleave a fluorogenic substrate, reporting through an increase in fluorescence emission at 570 nm. The third deoxyribozyme mimics an i(1)ANDi(2) gate and cleaves the other fluorogenic substrate, reporting through a...

<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique applied to implement a group half (HA) blocks architect the proposed adder. pipelined carry (PCA) method suitable for carrying out desired by using HA circuits XOR and AND gates. reduces critical path delay 27% compared with ripple (RCA) relatively lowers logic gates 55% loo...

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...

The shrinkage in size of VLSI chips as well as improved energy efficiency is the need of the modern digital era. Using ternary logic instead of conventional binary logic helps to reduce circuit complexity and hence reduces chip area. Carbon nanotubes FET (CNTFET) are preferred over CMOS for logic design due to its high performance i.e. excellent transport property, low resistivity and higher cu...

An algorithm for parallel multiplication of two n-bit ternary numbers is presented in this brief contribution. This algorithm uses the technique of column compression and computes the product in ( 2 [log, n1 + 2 ) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implement...

The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most them depend on batteries to operate. target this work is decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding over binary circuits (2) carbon nanotube field-effect transistors (CNFET) show better performance than CMO...

A fluidic one-bit half-adder is made of five channels which intersect at a junction. Two channels are inputs, two channels are outputs and one channel is the drain. The channels direct fluid from input fragments to output fragments and the streams of fluid interact at the junctions. Binary signals are represented by water droplets introduced in the input channels: presence of a droplet in an in...