With increasingly stringent requirements for memory test, the complexity of the test algorithm is increasing. This will make BIST (Build-In-Self-Test) circuit more complex and the area of BIST circuit larger. This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testin...

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K to 800K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Compar...

0026-2714/$ see front matter 2012 Elsevier Ltd. A http://dx.doi.org/10.1016/j.microrel.2012.09.013 Abbreviations: BIST, Built-In Self-Test; CLB, configu under test; D-FF, D flip-flop; EDA, electronic desig programmable gate array; IOB, input/output block; I integrated software environment; JTAG, joint test acti MVP, module verification platform; ORA, output respo component interface express; PI...

New BIST methodology for RTL data paths is presented. The proposed BIST methodology takes advantage of the structural information of RTL data path and reduces the test application time by grouping same-type modules into test compatibility classes (TCCs). During testing, compatible modules share a small number of test pattern generators at the same test time leading to significant reductions in ...

A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algori...

This thesis focuses on a digital Built-in Self-Test (BIST) approach to perform specification oriented testing of the analog portion of a mixed-signal system. The BIST utilizes a direct digital synthesizer (DDS) based test pattern generator (TPG) and a multiplieraccumulator (MAC) based output response analyzer (ORA) to stimulate and analyze the analog devices under test, respectively. This appro...

A Built-in Self-test (BIST) approach is presented for testing the programmable I/O cells in Field Programmable Gate Arrays (FPGAs). Using this approach, three BIST architectures and a total of 78 BIST configurations were developed to test the I/O cell logic resources and I/O buffers in all modes of operation in Xilinx Virtex-4 FPGAs. Each BIST configuration is valid for both bonded and unbonded...

The design and architecture of a memory test synthesis framework for automatic generation, insertion and veriication of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The exibility and eeciency of the framework are demonstrated by showing that memory BIST units with diierent architecture and characteristics could be...

ATPG vectors for a combinational circuit exhibit correlations among the bits of a test vector. We propose a BIST/decompressor circuit design methodology using spectral methods which utilizes the correlation information. This circuit serves dual purposes. It generates BIST vectors that are similar to the ATPG vectors with higher test coverage as compared to random and weighted random vectors. Th...

In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roug...