Problem Statement. Everyone will agree that a key issue in the design of multi-GHz interface devices is jitter performance. To characterize jitter performance, do you measure timing jitter or period jitter of the device? Should the Bit Error Rate performance of the device also be tested? Is there any way to shorten the overall test time? And as always, is there a way to reduce the test cost? Fu...

With the proliferation of commercial experiment generators and custom software within cognitive psychology and the behavioral sciences, many have assumed that issues regarding millisecond timing accuracy have been largely solved. However, through empirical investigation of a variety of paradigms, we have discovered numerous sources of timing error. These can range from poor scripting practices,...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

this study aims to better understand the effect of practice schedule and feedback providing types. in two separate experiments the contextual interference effect in bandwidth and self-control feedback conditions on relative and absolute timing learning was examined. in experiment i, the effect of contextual interference using bandwidth and self-control feedback on absolute timing learning (para...

Timing-accurate storage emulation offers a unique performance evaluation capability: the flexibility of simulation with the reality of experimental measurements. This allows a researcher to experiment with not-yet-existing storage components in the context of real systems executing real applications. As its name suggests, a timing-accurate storage emulator appears to the system to be a real sto...

As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. This paper explores the impacts of random and systematic process variations on SRAM cell stability and timing. The largest contributors to these robustness and timing ...