Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/ decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitanc...

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in 'ON' state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer...

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as biosensor to identify different protein molecules. Among plethora existing types biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs preferred over TFETs and JLFETs because their ease fabrication superior biosensing performance. ...

In this thesis innovative tunnel devices based on new architectures, new fabrication approaches and novel material combinations are fabricated and investigated in detail. In particular, nanowire homoand heterojunction tunnel diodes based on Si and InAs-Si have been demonstrated for the rst time. The gained knowledge and understanding of tunnel diodes is applied to design and fabricate InAs-Si h...

The Internet of Things (IoT) is becoming increasingly popular in areas like wearable communication devices, biomedical and home automation systems. IoT-compatible processors or devices need larger integrated memory circuits, static random access (SRAM). design such a with fast times low leakage challenge. In this article, we have proposed 7T SRAM cell using an InGaAs-dual pocket-dual gate-tunne...

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. high K insulation guarantees the proposed device to be used in low leakage memory systems. corresponding analytical model developed extract various parameters such as surface potential, ele...

Abstract In this work, we have implemented the step-shape double gate Tunnel FET (SSDG-TFET) biosensor, where nanogaps are embedded to work it as a biosensor. these nanogaps, biomolecules inserted By increasing dielectric constant (k) of from 5 12, sensitivity (Sn) is retrieved when neutral and positive/negative present. The influence k on switching ratios (ION/IOFF, ION/IAMBP) highlighted unde...

In this manuscript, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized. The designed configuration well optimized analyzed for different source thickness, length, drain length with lateral tunneling lengths between the edge dielectric. Also, we some stand-points like threshold voltage, ION to IOFF current ratio, ambipolar conduction range, sub-threshold swing va...

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the technology, while lookup tables (LUT) resulting from a physics model have applied TFET. To consider parasitic effects circuit performances, nm-based circuits laid out, included in TFET LUT implementat...

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nmthin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-n...