Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip f...

This work is devoted for the design and FPGA implementation of a 16bit Arithmetic module, which uses Vedic Mathematics algorithms. For arithmetic multiplication various Vedic multiplication techniques like Urdhva Tiryakbhyam Nikhilam and Anurupye has been thoroughly analyzed. Also Karatsuba algorithm for multiplication has been discussed. It has been found that Urdhva Tiryakbhyam Sutra is most ...

High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multifunctions and have multiplier as the critical element. In this paper, we present design and implementation of high speed and area efficient AU using Vedic algorithm. The work uses a simple “vertical and crosswise sutra” of Vedic mathematics to produce low complex...

High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth ...

This paper illustrates the simulation of Vedic multiplier in 2D DCT. The input data is first divided into NxN blocks, each block s of 8x8 size and 2-D DCT is applied on each of these 8x8 block and 2-D DCT is applied to reconstruct the image. The proposed 2-D DCT design uses Urdhva Tiryagbhyam a Vedic multiplication sutra and the Simulations with MATLAB prove that the proposed design is compared...

This paper proposes a method for area efficient fractional fixed point(Q-format) multiplier based on Urdhava Tiryakbhyam of vedic mathematics. Even though conventional or normal Urdhava multipliers carries high speed mathematical operations, they consume more chip area. Hence we proposed a pipelined multiplier architecture in this paper which consumes less chip area. The pipelined multiplier ar...

In present scenario every process should be rapid, efficient and simple. Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. It has great applications in communication, signal and image processing and instrumentation. But the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple it’s necessary for a multip...

High speed execution of arithmetic operations and high degree of precision in real time system are of major concern in any digital signal processing (DSP). Speed of DSP depends on speed of multiplier and algorithm used. In this paper we propose Residue Number System method for fast “carry free” floating point arithmetic operations. Floating Point RNS units have obvious advantages over tradition...

The Fast Fourier Transform (FFT) is most widely used in DSP such as imaging, signal processing, frequency communication, applied wireless system. In this paper, a reconfigurable DIT8 point FFT design using Vedic multiplier with small area and low power is presented. Urdhava Triyakbhyam algorithm, an ancient Vedic Indian Mathematics sutra, is utilized to achieve high throughput. In the proposed ...

Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in high computation throughput due to its replica architecture, where latency is mini...