This paper deals with a declarative interface for VHDL in general and the use of such an interface for OBDD based verification of VHDL gate level designs in particular. It presents a solution that enables OBDD verification without external manipulation of the netlist which is well integrated into the standard VHDL environment. The information required for OBDD based VHDL verification, existing ...

This paper presents a new platform for VHDL visualization to support undergraduates in learning this hardware description language. The presented platform, denoted as VISUAL-VHDL, enables students to enter their own VHDL code and control an animation process, which shows step-by-step how the different language constructs are treated to synthesize a complete digital circuit. Furthermore, VISUAL-...

This tutorial paper gives a functional semantics for delta delay VHDL i e VHDL restricted to zero delay signal assignments In combination with the sequential state ments zero delay signal assignment is su cient to generate the full algorithmic ex pressibility of VHDL The restriction is useful for a formal semantics of VHDL aimed at higher levels of abstraction where real absolute and precise ti...

This paper proposes VHDL-AMS syntax extensions that enable descriptions of AMS systems with partial differential equations. We named the extended language VHDL-AMSP. An important specific need for such extensions arises from the well known MEMS modelling difficulties where complex digital and analogue electronics interfaces with distributed mechanical systems. The new syntax allows descriptions...

A novel methodology for specification and synthesis of adaptive interfaces for Soft IP cores using the VHDL+ extension to VHDL is presented . Our approach separates the specifications of IP core functional behaviour and core interface into different design units. While the core functional behaviour is defined in form of a VHDL+ model that has a transaction level interface, the core interface sp...

∗ This work has been partially funded by TOMI project (ESPRIT #20724) Abstract: This paper describes a method to perform error simulation to estimate the quality of the testbenches used to validate VHDL designs. The method is based in the mutation of VHDL descriptions by an error model. The proposed method allows an automatic execution of the error simulation using a commercial VHDL simulator. ...

Goossens defined structural operational semantics for a subset of VHDL-87 and proved that the parallelism present in VHDL is benign. We extend this work to include VHDL-93 features such as shared variables and postponed processes that change the underlying semantic model. In the presence of shared variables, nondeterministic execution of VHDL-93 processes destroys the unique meaning property. W...