For my MSc project at the Computer Engineering Laboratory at Delft University of Technology I will design and implement a reconfigurable Very Large Instruction Word (VLIW) processing core, for use within the Molen[6, 9] reconfigurable processing paradigm. The Instruction Set Architecture (ISA) used for this processing core will be VEX[2] (VLIW Example), which is loosely modeled on the ISA of th...

Reducing code size is crucial in embedded systems as well as in high-performance systems to overcome the communication bottleneck between memory and CPU, especially with VLIW (Very Long Instruction Word) processors that require a high-bandwidth instruction prefetching. This paper presents a new approach for dictionary-based code compression in VLIW processor-based systems using isomorphism amon...

Presented is an 8-issue tree-VLIW processor designed for efficient support of dynamic binary translation. This processor confronts two primary problems faced by VLIW architectures: binary compatibility and branch performance. Binary compatibility with existing architectures is achieved through dynamic binary translation which translates and schedules PowerPC instructions to take advantage of th...

Instruction Level Parallelism (ILP) machines, such as Very Long Instruction Word (VLIW) architectures, and customised architectures are two paradigms that are used to increase the performance of processors. While a VLIW machine has multiple functional units, a customised processor is equipped with Application-specific Functional Units (AFUs). Customisation has been proved beneficial on single i...

Statically scheduled machines do have a disadvantage when dealing with dynamic events, such as cache hit or miss detection. Early VLIW machines were designed without caches, to achieve predictability in memory access. However, such designs suffer in memory performance. To achieve high performance, VLIW architectures must have adequate support for using caches. A simple VLIW design might use an ...

Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explici...

This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing dynamically scheduled Very Long Instruction Word (VLIW) instructions. Dynamically Instruction Scheduled VLIW (DISVLIW) processor is aimed specifically at dynamic scheduling VLIW instructions with dependency information. The DISVLIW processor dynamically schedules each instruction w...

 Dynamically Trace Scheduled VLIW (DTSVLIW) machines have two execution engines and two instruction caches: a Scheduler Engine and a VLIW Engine, and an Instruction Cache and a VLIW Cache. The Scheduler Engine fetches instructions from the Instruction Cache and executes them singly, the first time, using a simple pipelined processor. In addition, it dynamically schedules the instruction trace ...

 Due to the temporal execution locality present in programs, even small instruction caches (16-Kbyte) can provide processors with fast access to instructions most of the time. The Dynamically Trace Scheduled VLIW (DTSVLIW) architecture exploits programs’ temporal execution locality by executing code in two distinct modes. In the first execution encounter, fragments of the code are executed in ...